00:00hello everyone and welcome to lecture
00:04my name is Arash Ptolemy and I'm working
00:07with Professor Anant Agarwal at the
00:10Department of Electrical and Computer
00:11Engineering at the Ohio State University
00:14now first of all I would like to thank
00:17poinar for founding this lecture series
00:19on course on silicon and silicon and
00:22wide bandgap power devices I also want
00:26to thank professor wound a song at sunny
00:28poly for sharing some information to all
00:32with us for preparing these slides in
00:37the previous lecture I explained how can
00:39we form all these fingers with different
00:43doping concentration in order to make
00:46that n plus source P plus P l jf ed and
00:51so on but one thing that is so important
00:55as I mentioned the GPS as well after the
00:58implantation we need to activate all
01:01these dopants in order to contribute
01:06electrically in the device for this case
01:10we need to anneal the sample and as I
01:14mentioned in the JPS lecture we need a
01:18cap layer before anything so for making
01:22cap layer before the end link we can
01:25coat the sample with for example
01:28photoresist and then annalee it at
01:31higher temperature in order to make a
01:33graphite cap layer so in this case we
01:36need for example for micrometers
01:38graphite cap layer over the sample and
01:42then by this cap layer we can use high
01:49temperature any link organ ambient 1700
01:52degrees C for 30 minutes in order to
01:55activate all these dopants and after the
01:59activation we can remove this cap layer
02:02carbon cap layer by oxygen plasma
02:08the next step is oxide deposition we can
02:14deposit the oxide board but after all
02:17this implantation and normally we have
02:21bad surface morphology on the surface so
02:24in order to improve the surface
02:25morphology we can use the sacrificial
02:28oxidation in this case we grow oxide in
02:32a thermal oxide on the surface at high
02:35temperature and then remove this oxide
02:39by buffer achieve or HF so for example
02:43we can have a 20 nanometer sacrificial
02:47oxidation and then by buffer chip we can
02:49remove it and now we can deposit oxide
02:5350 nanometer trioxide growth at 1200
02:56degree C now after the oxide deposition
03:00we have post and link at 12 1200 degrees
03:04C first in argon ambient for one over
03:07and then N or ambient for two hours this
03:11step passivation actually is very very
03:14important and critical for these devices
03:18in order to achieve a better and higher
03:21channel mobility otherwise we will have
03:23a lot of scattering at the surface and
03:27then the mobility channel mobility will
03:29decrease so and all is being used in
03:34order to passivate the dangling bonds at
03:36the surface other gases such as into aw
03:40or n 2o can be used as well but n or n
03:44link has better result for silicon
03:53after the passivation then we need to
03:59grow poly silicon or the oxide in this
04:03case we can deposit 500 nanometers poly
04:06silicon utilizing lpcvd low pressure
04:10chemical vapor deposition and then we
04:14can dubbed it viet phosphorus over the
04:18oxide and now we need to form the poly
04:25silicon in order to have the gate poly
04:27over the gate so here is the channel
04:32right so the gate would be over here on
04:37the channel between the n plus source
04:39and japheth in the left-hand side of
04:42this cell and right-hand side of another
04:46cell for this step policy poly silicon
04:54can be etched utilizing it photoresist
04:58mask so we coat the sample with
05:01photoresist using lithography a mask
05:05exposure exposing and developing then we
05:08have suitable mask and then we can
05:10dry-aged the poly silicon and after that
05:14we can remove the photoresist by oxygen
05:17plasma or acetone now let's look at the
05:23gate poly as you can see here the right
05:26hand side is the whole device I assumed
05:30this box to here so we have this gate
05:36pad over here and all these fingers and
05:39if you look at this box we have three
05:43point three micrometers distance between
05:45the fingers with a width of 4
05:47micrometers so here we have 4 micrometer
05:51gate poly or poly silicon over the this
05:56source and channel japheth channel and
06:03this is a actually combination of PL and
06:07plus source P plus and gate poly all
06:10together so let's look at this part we
06:15have the gate Holi or here for micro
06:19meters similar to this cross-sectional
06:21view so 0.5 micrometer 0.5 micrometer we
06:26have the over layers sorry overlap of
06:29the N plus stores this part is so
06:32important the overlap suppose that we
06:35don't have any overlap then if we have
06:37an misaligning for example suppose there
06:40we have 1 micrometer of missile on e to
06:43the right hand side then the polysilicon
06:46could be a start from this point to the
06:49right hand side in this case we don't
06:53have any gate or the channel and if we
06:55don't have any gate or the channel it
06:57means that we don't have any current in
06:59the left hand side this overlap tip
07:03actually relates on the resolution of
07:07the little graffia step that you are
07:09using if you for example using a stepper
07:11with 0.5 micrometer resolution then you
07:15need at least point 5 micrometer over
07:18layer here as I mentioned here we can
07:29see PL and plus source P plus and gate
07:33poly but at the periphery of the device
07:37so as you remember we have a void region
07:41of P plus 450 5 micro meter width in
07:44order to our rounding corners then over
07:47that with 48 micro meter width we have
07:51also Dec gate or polysilicon
07:55or the P plus and in the left hand side
08:00for show we have the active area in the
08:03middle part of the device
08:11after the gate Polly informing the gate
08:15we need to deposit oxide or them so one
08:21micrometer silicon dioxide can be
08:23deposited by PECVD and then by red oxide
08:28growth at 950 degree C for one hour we
08:32are doing the densification again we are
08:34not growing any actually oxide that
08:36growth rate is negligible
08:38we are just densify the oxide that we
08:41have deposited in order to a better
08:42quality and over the oxide silicon
08:46dioxide we are depositing 200 nanometer
08:50silicon nitride by lpcvd in order to
08:54have a moisture suitable moisture
08:56barrier mass number 7 is a metal over
09:04the source and also people us or here
09:10and here for this step for sure we need
09:17a photolithography coating sample via
09:20photoresist exposing developing and
09:22after that we can oxide and we can dry
09:26the oxide I edge of the arc say silicon
09:29nitride and silicon dioxide utilizing
09:31this photoresist mask and then we have
09:37this opening windows for depositing
09:42nickel but one thing is so important
09:44when you edge the oxide and reach to the
09:47silicon carbide you need to put the
09:50sample as soon as possible in the
09:52evaporator otherwise
09:54silicon dioxide will grow on the surface
10:01and then we are putting or depositing
10:04nickel or the oxide instead of silicon
10:08carbide so native oxide is so important
10:12to be prevented so after putting the
10:18sample in the evaporator we can deposit
10:23nanometer or nickel and then we can use
10:28arterial rapid thermal annealing at 600
10:31degree C one thing that is so important
10:35over here is actually we are depositing
10:40right over the silicon carbide surface
10:44and also over this oxide silicon nitride
10:48here when we are doing the rapid thermal
10:52annealing at 600 degrees C this nickel
10:57make a nickel silicide with the silicon
11:02carbide surface at the surface of the
11:03silicon carbide but there is no reaction
11:06between nickel and silicon nitride or
11:09silicon dioxide or here so if we use for
11:15example piranha we can remove the nickel
11:20over the silicon nitride easily but
11:26nickel silicide cannot be removed so
11:31here we are removing an silicide medal
11:35on the oxide and also we have nickel
11:40on the silicon carbide however 600
11:44degree C is not enough temperature in
11:48order to have a good ohmic contact in
11:52this lecture in this paper we showed
11:57that at 600 degree C we have a peak of
12:01nickel silicide but the intensity of
12:05this peak is not enough to have a good
12:09so now after the room removing the
12:13unsolicited part of the nickel we can
12:18have the second step and link so here is
12:22the first step annealing at 600 degrees
12:24C but after removing the unsolicited we
12:27can have the N link or the second step
12:30aniline at higher temperature 900 or 950
12:36degree C in order to increase the
12:39intensity of the nickel silicide and
12:41when the nickel silicide intensity of
12:43the nickel silicide is increased it
12:45means that we have a better with our me
12:47contact and lower resistivity I
12:50encourage you to read this paper that we
12:55published at kth in Sweden here is mass
13:04layout arming metal as I taught we have
13:11the nickel in the active area different
13:14all fingers are in parallel then we have
13:182.3 micrometers width of these nickels
13:22with a distance or gap between them is 5
13:25micrometer as you can see also here this
13:32is a combination of mass layered between
13:34gate poly and on metal so here in the
13:39zoom part we have all these great poly
13:45we formed for micro meters and 2.3 micro
13:49meters 2.3 micro meters is the nickel
13:53over here and for micro meter is the
13:55width of 10 plus poly silicon over here
13:59and as I mentioned we have it actually
14:060.5 micrometer distance profile
14:10micrometer distance between the gate
14:18next step is backside our metal in order
14:21to have a good ohmic contact at the
14:23backside so in this case we are coating
14:26the top side with the photoresist and
14:30then using oxide with a in order
14:39to remove all native oxides on the
14:42backside then after that we need to
14:48remove the photoresist as well and then
14:53deposit 114 million nanometer nickel the
14:57backside then by RTA rapid thermal
15:01annealing at 950 degree scene and to
15:04ambient for one minute we will have a
15:06good ohmic contact by making a nickel
15:10silicide in the backside mass number
15:16eight is the gate runner its it cannot
15:18be seen in the cross-sectional view so
15:22here is the mask and from the topside so
15:25here is the gate pad and then we have a
15:28gate runner in the periphery so in this
15:34case actually we are opening the oxide
15:37or making via for the gate pad area so
15:43you see a combination of gate Polly and
15:47Polly gate together here is the gate
15:51runner at the middle so again we are
15:57just opening the oxide because we have
16:00oxide everywhere we are just open the
16:03window for these gates runners 10
16:08micrometers with here 10 micrometer with
16:12over here and then 28 micrometers with
16:16in the left left hand side
16:22so now we have the overlayer medal as I
16:26mentioned 4 micrometer thick aluminum
16:28can be used as a top medal in order to
16:32have a good kind of spreading so in this
16:36case we are spider sputtering aluminum 4
16:40micrometer aluminum sputtering then for
16:43using photoresist this photoresist and
16:46lithography we can use the aluminum wet
16:50etching in order to edge to this part of
16:55the aluminum that we don't need it and
16:57then by photos a stripping we can remove
17:01the photoresist and have aluminum over
17:03the gate and nickel army contact here is
17:09the mask here is the pad agate pad and
17:14source pad and as you can see all these
17:18corners have been rounded properly in
17:23the distance between this source pad and
17:27gate pad is 15 micrometers so here is
17:36aluminum or the gate and nickel and here
17:43is the aluminum in the periphery for the
17:47gate runner that we actually etch the
17:50oxide and reach the gate poly and then
17:54we have the aluminum here also you can
18:01see the aluminum here and here the
18:06people as an overlay metal and then we
18:12have the gate poly and over layer middle
18:21here is the combination of gate poly
18:24gate runner and overlayer metal so you
18:26see here is the gate runner that we
18:29opened the oxide reach to the
18:34polysilicon and over that we have this
18:38aluminum over the gate runner with an
18:43over layer of 5 micrometers in the right
18:45hand side and 5 micrometers in the left
18:47hand so in order to be sure that
18:49aluminum is connected to the gate poly
18:52here and again as I mentioned we have 15
18:57micrometers distance between the gate
18:59runners at the periphery and the
19:03aluminum and the source path so finally
19:10we have poly imide 7 micro meter
19:14polyamide in order to have a dielectric
19:16isolation and here we are just coating
19:21the material that the sample a 7
19:24micrometer polyamide then by utilizing
19:27photoresist lithography photoresist
19:31exposing developing then we can use this
19:35photoresist as a mask in order to dry
19:41etching of polyamide and here is the
19:45sample after the ROI arching and then we
19:49can easily remove the photoresist by
19:52stripping oxygen plus more acetone here
19:57you see the mass lay out from the top
19:59side gate pad and source pad and here is
20:05the distance 45 micro meters distance
20:08between them and the gate pad size is
20:13200 206 micrometers by 263 micrometers
20:18so this is the size of the gate pad and
20:21all these corners as you can see have
20:25been properly rounded
20:34the next step is backside over layer
20:37middle in order to have a good kind of
20:40spreading on the backside as well as I
20:43mentioned in the previous lecture in
20:46this case we can deposit a stack layer
20:49of tie or titanium nickel and silver
20:53with stack ratio of 50 300 and 100
20:58nanometers so by this actually I explain
21:06all these masks ten masks from the
21:09alignment mark Japheth implantation PL n
21:12plus source and P plus and then
21:15activation or activating the all these
21:18doping concentrations or docking and
21:21events and then gate poly on middle gate
21:24runner over layer middle and polymer and
21:26here is the all masks together for
21:33device via 2.1 millimeter square you can
21:37see the gate pad to source pad at the
21:40middle with 46 chord rings and then we
21:43have the channel list of n plus channel
21:45stop at the periphery of the device
21:49thank you very much for your attention
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